Power Distribution Board · Steve Nketiah

Overview

This project started off as a brake chopper for my FOC board to prevent it from destroying my power supply. It has now turned into a power distribution board capable of powering three boards, and I plan on using it in future robotics projects.

3D render of the power distribution board with a large connector on the left, eight bulk capacitors in the middle and three connectors plus a two-way screw terminal on the right — PCB render.

Design goals

Handle 60 V / 30 A
Measure bus voltage and current
Include a brake chopper

Precharge circuitry

A high-side MOSFET limits inrush into the bus. The gate driver sources a constant ~60 µA into the gate, which has a capacitor ($C_{dv/dt}$) to ground, so the bus rises at a fixed rate of $I_{\mathrm{gate}} / C_{dv/dt}$ regardless of bus voltage or load. During this ramp the MOSFET operates in its linear region with a high $V_{DS}$, which would put a standard switching MOSFET outside its safe operating area, so I selected a MOSFET rated for linear-mode operation (wide SOA). The simulations below (55 V input, 2.8 mF bus capacitance, 3 W logic load turning on at 9 V) show the effect of $C_{dv/dt}$. I chose 470 nF: peak inrush is ~0.67 A, the MOSFET peaks at ~32 W for a fraction of a second (~5.5 J total), and startup takes ~0.46 s.

LTspice schematic of the precharge circuit: 55 V source, MOSFET M1 with a 12 V zener from gate to source, 60 µA gate current source with 1 kΩ and Cdvdt to ground, and the bus capacitance, a 4.7 kΩ resistor and the logic load on the output — LTspice schematic of the precharge circuit. C_dvdt is stepped through 100 nF, 270 nF, 470 nF and 1 µF.

Simulation results. Traces: 100 nF 270 nF 470 nF 1 µF

Simulated bus voltage V(out) ramping from 0 to 55 V; the ramp gets slower as Cdvdt increases — Bus voltage, V(out). A larger C_dvdt gives a slower, linear ramp.

Simulated supply current I(V1) for each Cdvdt; peak inrush falls from about 2 A at 100 nF to about 0.5 A at 1 µF — Supply current, I(V1). It is negative because LTspice measures current into the source.

Simulated power dissipated in the MOSFET for each Cdvdt; peak falls from about 90 W at 100 nF to about 23 W at 1 µF — Power dissipated in the precharge MOSFET.

Result summary

Trace	C_dvdt	Peak supply current	Peak MOSFET power	Charge time
Green	100 nF	~2.0 A	~90 W	~0.10 s
Blue	270 nF	~0.93 A	~42 W	~0.27 s
Red	470 nF	~0.67 A	~32 W	~0.46 s
Cyan	1 µF	~0.48 A	~23 W	~0.98 s

Brake chopper circuitry

The brake chopper is based on a comparator. A divided-down copy of $V_{\mathrm{BUS}}$ is fed into the non-inverting input, and a reference voltage generated by the MCU is fed into the inverting input. When $V_{\mathrm{BUS}}$ exceeds the set voltage, the comparator output goes high and turns on the chopping MOSFET. This dumps the excess energy into the brake resistor, pulling the bus voltage back down. I added hysteresis to the comparator, so once the chopper turns on it stays on until the bus falls below a lower threshold. This prevents it from chattering around the set point. Below are my calculations for the divider and hysteresis resistors.

Comparator circuit: V_BUS divided by R_top and R_bot into the non-inverting input of a TLV1805, V_REF from the MCU on the inverting input, and R_fb from the output back to the non-inverting input for hysteresis — Non-inverting comparator with resistive hysteresis (TLV1805, push-pull, $V_{CC} = 12\,\mathrm{V}$). Output high turns the brake MOSFET on.

Threshold derivation

The comparator switches when $V_+ = V_{\mathrm{REF}}$. KCL at $V_+$:

$$\frac{V_{\mathrm{BUS}} - V_{\mathrm{REF}}}{R_{\mathrm{top}}} + \frac{V_{\mathrm{OUT}} - V_{\mathrm{REF}}}{R_{\mathrm{fb}}} = \frac{V_{\mathrm{REF}}}{R_{\mathrm{bot}}}$$

$$\Longrightarrow\quad V_{\mathrm{BUS}} = V_{\mathrm{REF}}\underbrace{\left(1 + \frac{R_{\mathrm{top}}}{R_{\mathrm{bot}}} + \frac{R_{\mathrm{top}}}{R_{\mathrm{fb}}}\right)}_{K} \;-\; V_{\mathrm{OUT}}\,\frac{R_{\mathrm{top}}}{R_{\mathrm{fb}}}$$

Chop and release thresholds

$$\begin{aligned} \textbf{Chop}\ (\text{bus rising, } V_{\mathrm{OUT}} = 0):&\quad V_{\mathrm{CHOP}} = K\, V_{\mathrm{REF}} \\[2pt] \textbf{Release}\ (\text{bus falling, } V_{\mathrm{OUT}} = V_{CC}):&\quad V_{\mathrm{REL}} = V_{\mathrm{CHOP}} - V_{\mathrm{HYS}} \\[2pt] \textbf{Hysteresis}:&\quad V_{\mathrm{HYS}} = V_{CC}\,\frac{R_{\mathrm{top}}}{R_{\mathrm{fb}}} \end{aligned}$$

Component selection

Target $V_{\mathrm{HYS}} = 1.2\,\mathrm{V}$ with $V_{CC} = 12\,\mathrm{V}$.

Feedback ratio.
$$\frac{R_{\mathrm{top}}}{R_{\mathrm{fb}}} = \frac{1.2\,\mathrm{V}}{12\,\mathrm{V}} = 0.1 \;\Rightarrow\; R_{\mathrm{top}} = 100\,\mathrm{k\Omega},\;\; R_{\mathrm{fb}} = 1\,\mathrm{M\Omega}$$
Divider ratio. For $V_{\mathrm{CHOP}} = 36\,\mathrm{V}$ at mid-scale $V_{\mathrm{REF}} = 1.65\,\mathrm{V}$:
$$\frac{36}{1.65} = 1 + \frac{100\,\mathrm{k\Omega}}{R_{\mathrm{bot}}} + 0.1 \;\Rightarrow\; \frac{100\,\mathrm{k\Omega}}{R_{\mathrm{bot}}} = 20.718 \;\Rightarrow\; R_{\mathrm{bot,ideal}} = 4.83\,\mathrm{k\Omega}$$
Standard value. Choosing E24 $R_{\mathrm{bot}} = 4.7\,\mathrm{k\Omega}$:
$$K = 1 + \frac{100\,\mathrm{k\Omega}}{4.7\,\mathrm{k\Omega}} + \frac{100\,\mathrm{k\Omega}}{1\,\mathrm{M\Omega}} = 1 + 21.277 + 0.1 = \mathbf{22.377}$$

Design equations

$$V_{\mathrm{CHOP}} = 22.377\, V_{\mathrm{REF}} \qquad V_{\mathrm{REF}} = \frac{V_{\mathrm{CHOP}}}{22.377} \qquad V_{\mathrm{REL}} = V_{\mathrm{CHOP}} - 1.2\,\mathrm{V}$$

Reference voltage

Since the MCU I chose doesn’t have a DAC, I generate a PWM signal using a timer and filter it with a first-order low-pass filter. I chose R = 10 kΩ and C = 4.7 µF. This gives a cutoff frequency of 3.39 Hz and a time constant of 47 ms (about 0.24 s to settle), which balances settling time against ripple on the threshold.

RC low-pass filter: PWM from the MCU timer through a 10 kΩ resistor to the V_REF node, with a 4.7 µF capacitor to ground

$$f_c = \frac{1}{2\pi RC} = \frac{1}{2\pi\,(10\,\mathrm{k\Omega})(4.7\,\mu\mathrm{F})} = 3.39\,\mathrm{Hz}, \qquad \tau = RC = 47\,\mathrm{ms}$$

Ripple on the chopping voltage. With a PWM period much shorter than $\tau$, the peak-to-peak ripple on $V_{\mathrm{REF}}$ at duty $D$ is approximately

$$\Delta V_{\mathrm{REF}} \approx \frac{V_{DD}\, D(1-D)}{f_{\mathrm{PWM}}\,\tau} \;\le\; \frac{V_{DD}}{4\, f_{\mathrm{PWM}}\,\tau}$$

and the divider multiplies it by $K$ at the bus:

$$\Delta V_{\mathrm{CHOP}} = K\,\Delta V_{\mathrm{REF}} \;\le\; \frac{22.377 \times 3.3\,\mathrm{V}}{4\, f_{\mathrm{PWM}} \times 47\,\mathrm{ms}} \approx \frac{393\,\mathrm{V \cdot Hz}}{f_{\mathrm{PWM}}}$$

Calibration

Since I only have 1% resistors, the threshold can be off by about ±1.6 V. To fix this, I plan on calibrating the chopper threshold with a multimeter and storing the calibration values in code. Here is how the calibration works:

Set CCR = 2400 (ARR = 2399, so 100% duty and $V_{\mathrm{REF}} = V_{DD}$). This puts $V_{\mathrm{CHOP}}$ at about 74 V, so the chopper stays off during calibration.
Apply a known bus voltage $V_{\mathrm{cal}}$, for example 48 V, read from the bench supply or a DMM.
Average 16–64 ADC samples of $V_+$ to get $\mathrm{code_{cal}}$.
Store $V_{\mathrm{cal}}$ and $\mathrm{code_{cal}}$ in flash.

Then set the threshold with:

$$\mathrm{CCR} = \frac{V_{\mathrm{CHOP}} \cdot \mathrm{code_{cal}} \cdot (\mathrm{ARR} + 1)}{V_{\mathrm{cal}} \cdot 4095}$$

Because the ADC reads the same node the comparator sees, and both the ADC and the PWM reference $V_{DD}$, the divider tolerance and $V_{DD}$ cancel out of this formula.

Voltage and current measurement

To measure the bus voltage, I use a separate voltage divider to step down $V_{\mathrm{BUS}}$ so it can be fed into the STM32 ADC.

For the current measurement, I use a 2 mΩ shunt resistor with an INA240A1D current-sense amplifier, whose output is read by the STM32 ADC.

Verification

Hardware verification is in progress. I will add the results here once I verify them on the board.

PCB designPower electronicsLTspiceAnalog designSTM32